Low Power, Delay Optimised Buffer Design using 70nm CMOS Technology
نویسندگان
چکیده
This paper addresses the issues of power dissipation and propagation delay in CMOS buffers driving large capacitive loads and proposes a CMOS buffer design for improving power dissipation at optimized propagation delay. The reduction in power dissipation is achieved by minimising short circuit power and subthreshold leakage power which is predominant when
منابع مشابه
Low Power, Delay Optimized Buffer Design using 70nm CMOS Technology
This paper addresses the issues of power dissipation and propagation delay in CMOS buffers driving large capacitive loads and proposes a CMOS buffer design for improving power dissipation at optimized propagation delay. The reduction in power dissipation is achieved by minimizing short circuit power and subthreshold leakage power which is predominant when supply voltage (VDD) and threshold volt...
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